Configurable Logic Core

The eASICore is a high performance and high-density configurable logic core aimed at accelerating the development cycle and supporting derivatives for platform-based designs and System-on-Chip (SoC). The device has Standard Cell compatible performance and delivers the benefits of fast–turnaround configurable core in a cost saving approach. The logic core provides designers with a flexible and friendly design environment together with the means of getting first to market. It is ideally suited for use in platform-based designs.

The core's architecture is based on proprietary technology that provides an efficient solution for embedding configurable logic blocks in a fast, easy to implement and cost-effective method. This technology is rooted in a concept of combining an SRAM Look-Up-Table cell with metal mask programmable interconnection. This combination allows delivering close to Standard Cell performance and density together with FPGA time-to-market and ease-of-design. The technology addresses the issues of huge silicon area and circuit delay resulted from the programmable routing in existing FPGA devices.

Features:

• It can be ported across conventional silicon fabrication processes and is flexible for use at various target foundries.
• Each logic core is 25K gate module, about 1mm sq.
• Configurable as: High logic density of ~30,000gate/mm² & Dual Port SRAM at 40K bit/mm²
• As low as 7 day customization turnaround time
• NRE cost of one to three masks (instead of ~30 masks used for Standard Cell customization)
• Performance: compatible with Standard Cell, system clock speed of over 500 MHz
• Debugging Friendly: Easy reload of Look-Up-Table for debugging purpose. Full observability by using scan-chain
• SoC Friendly: Multiple cores can be tiled and integrated to build the required size of programmable logic.

eASIC Corporation, 3555 Woodford Drive, San Jose, CA 95124. Tel: 408-264-7128; Fax: 408-264-7193.